ESP32-S31

SoC
by Espressifesp32-s31
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Specifications

Radios

Wi-Fi
Wi-Fi 6 · 2.4 GHz
Bluetooth LE
BLE 5.4
Bluetooth Classic
yes
802.15.4
Thread 1.4, Zigbee 3.0

USB

Native USB
yes
USB type
usb-2.0-high-speed-otg + serial-jtag

CPU

Architecture
risc-v
Cores
2
Max clock
320 MHz
Extensions
fpusimd-vector
Low-power core
risc-v @ 40 MHz

Memory

SRAM
512 KB
LP SRAM
32 KB
ROM
320 KB
In-package PSRAM options
16 MB, 32 MB
External PSRAM
yes

Interfaces

Peripherals
ethernet-mac-1000mbps-rmii-miidvp-camera-8to16bitlcd-parallel-rgb-i8080-moto6800-8to24bitcapacitive-touch-14chi2s-dual

Security

Features
secure-bootflash-psram-encryption-xts-aesaessharsaecchmacrsa-ecdsa-dstrngpufsecure-debug-controllerkey-managerapmteeglitch-detector

Dual-core RISC-V @ 320 MHz with SIMD/FPU, Wi-Fi 6, Bluetooth 5.4 (LE + Classic), 802.15.4 (Thread/Zigbee), and an integrated 1000 Mbps Ethernet MAC -- Espressif's newest multi-protocol HMI/connectivity chip.

Frequently asked questions

What are the ESP32-S31 specs / datasheet?

ESP32-S31 is a dual-core RISC-V SoC clocked up to 320 MHz, plus a separate low-power RISC-V core up to 40 MHz. It has 512 KB of SRAM (32 KB in the LP domain) and 320 KB of ROM. Radios: Wi-Fi 6, Bluetooth LE 5.4, and an 802.15.4 radio. It exposes native USB (Serial/JTAG).

What is the ESP32-S31 pinout / GPIO count?

The ESP32-S31 has 60 GPIO pads in total, of which 3 are strapping pins and 8 are tied to USB/flash.

What wireless radios does the ESP32-S31 have?

ESP32-S31's wireless radios: Wi-Fi: Wi-Fi 6 radio. Bluetooth: Bluetooth LE 5.4. 802.15.4: 802.15.4 radio (thread-1.4, zigbee-3.0).

Does the ESP32-S31 have a low-power (LP) core?

Yes -- the ESP32-S31 has a separate RISC-V low-power core clocked up to 40 MHz, alongside its main core (up to 320 MHz).

ESP32-S31 vs ESP32-S2: what's different?

The ESP32-S31 is a dual-core RISC-V SoC at up to 320 MHz (512 KB SRAM); the ESP32-S2 is a single-core Xtensa LX7 SoC at up to 240 MHz (320 KB SRAM). Wi-Fi: Wi-Fi 6 vs Wi-Fi 4. Bluetooth: BLE 5.4 vs no BLE. 802.15.4: 802.15.4 yes vs 802.15.4 no. Low-power core: LP core yes vs LP core no.

Notes

  • Wi-Fi 6 (802.11ax), 2.4 GHz only, 1T1R; backward compatible with 802.11b/g/n up to 150 Mbps
  • Bluetooth 5.4 with both LE (Mesh 1.1, LE Audio, Direction Finding AoA/AoD, PAwR) and Classic BR/EDR
  • Integrated 1000 Mbps Ethernet MAC (RMII/MII); needs an external PHY
  • In-package octal PSRAM (16 or 32 MB) is not bonded out to separate GPIOs; the chip also supports external flash/PSRAM (up to 256 MB flash, 64 MB PSRAM) via SPI/Dual/Quad/Octal
  • No per-pad IOH/IOL current table published in the datasheet as of 2026-08-26 -- gpio_source_ma_max/gpio_sink_ma_max omitted, not guessed. gpio_pads_total=60 is the datasheet's stated GPIO count (8 LP GPIO + 52 HP GPIO).
  • Default drive strength: GPIO33/34 = 40 mA, others 20 mA (DRV levels 0-3 correspond to ~5/10/20/40 mA).
  • GPIO33/34 are USB Serial/JTAG D-/D+ by default; GPIO36-38,40-42 are tied to the off-package SPI flash (SPICS/SPIQ/SPIWP/SPIHD/SPICLK/SPID); GPIO37 doubles as both a strapping pin and the flash SPIQ signal.
  • No physically input-only GPIO stated in the Hardware Design Guidelines (GPIO13/RMII_CLK is input-only only in that one alternate function, not an inherent pad limitation) -- input_only omitted, not guessed.